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You searched IISERK - Subject: Computer networks.
| Tag |
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In 2 |
Data |
| 001 | | | vtls000012107 |
| 003 | | | IISER-K |
| 005 | | | 20140514150200.0 |
| 006 | | | m d |
| 007 | | | cr cn||||||||| |
| 008 | | | 090617m20039999ne a sb 001 0 eng d |
| 020 | | | \a 9781558608757 |
| 020 | | | \a 1558608753 |
| 037 | | | \a 97135:97135 \b Elsevier Science & Technology \n http://www.sciencedirect.com |
| 039 | | 9 | \a 201405141502 \b VLOAD \y 200906171857 \z VLOAD |
| 049 | | | \a TEFA |
| 082 | 0 | 4 | \a 621.395 \2 22 |
| 245 | 0 | 0 | \a Network processor design \h [electronic resource] : \b issues and practices / \c edited by Patrick Crowley ... [et al.]. |
| 260 | | | \a Amsterdam ; \a Boston : \b Morgan Kaufmann Publishers, \c c2003- |
| 300 | | | \a v. <1-> : \b ill. ; \c 24 cm. |
| 504 | | | \a Includes bibliographical references and index. |
| 505 | 0 | | \a Preface -- Chapter 1. Network Processors: An Introduction to Design Issues, Patrick Crowley, Mark Franklin, Haldun Hadimioglu, and Peter Onufryk -- Part 1. Design Principles -- Chapter 2. Benchmarking Network Processors, Prashant R. Chandra, Frank Hady, Raj Yavatkar, Tony Bock,Mason Cabot and Philip Mathew -- Chapter 3. A Methodology and Simulator for the Study of Network Processors, Deepak Suryanarayanan, Gregory T. Byrd and John Marshall -- Chapter 4. Design Space Exploration of Network Processor Architectures, Lothar Thiele, Samarjit Chakraborty, Matthias Gries and Simon Künzli -- Chapter 5. Compiler Back-end Optimizations for Network Processors with Bit Packet Addressing, Jens Wagner and Rainer Leupers -- Chapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization, Mark A. Franklin and Tilman Wolf -- Chapter 7. A Benchmarking Methodology for Network Processors, Mel Tsai, Chidamber Kulkarni, Christian Sauer, Niraj Shah and Kurt Keutzer -- Chapter 8. A Modeling Framework for Network Processor Systems, Patrick Crowley and Jean-Loup Baer -- Part 2. Practices -- Chapter 9. An Industry Analyst's Perspective on Network Processors, John Freeman -- Chapter 10. Agere Systems - Communications Optimized PayLoadPlus Network Processor Architecture, Bill Klein -- Chapter 11. Cisco Systems - Toaster 2, John Marshall -- Chapter 12. IBM - PowerNP Network Processor, Mohammad Peyravian, Jean Calvignac and Ravi Sabhikhi -- Chapter 13. Intel Corporation - Intel ʼ IXP2400 Network Processor: A 2nd Generation Intel ʼ NPU, Prashant Chandra, Sridhar Lakshmanamurthy and Raj Yavatkar -- Chapter 14. Motorola - C5e Network Processor, Eran Cohen Strod and Patricia Johnson -- Chapter 15. PMC-Sierra, Inc - ClassiPI, Vineet Dujari, Remby Taas and Ajit Shelat -- Chapter 16 TranSwitch - ASPEN: Flexible Network Processing for Access Solutions, Subhash C. Roy. |
| 520 | | | \a As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. Network Processor Design: Issues and Practices is an essential reference on network processors for graduate students, researchers, and practicing designers. * Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University. * Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch. |
| 533 | | | \a Electronic reproduction. \b Amsterdam : \c Elsevier Science & Technology, \d 2007. \n Mode of access: World Wide Web. \n System requirements: Web browser. \n Title from title screen (viewed on Aug. 2, 2007). \n Access may be restricted to users at subscribing institutions. |
| 650 | | 0 | \a Microprocessors. |
| 650 | | 0 | \a Application-specific integrated circuits. |
| 650 | | 0 | \a Computer networks \x Equipment and supplies. |
| 655 | | 7 | \a Electronic books. \2 local |
| 700 | 1 | | \a Crowley, Patrick, \d 1974- |
| 710 | 2 | | \a ScienceDirect (Online service) |
| 776 | 1 | | \c Original \z 1558608753 \z 9781558608757 \w (DLC) 2002108919 \w (OCoLC)51177543 |
| 856 | 4 | 0 | \3 ScienceDirect \u http://www.sciencedirect.com/science/book/9781558608757 \z An electronic book accessible through the World Wide Web; click for information \y An electronic book accessible through the World Wide Web; click for information \y ScienceDirect |
| 856 | 4 | 2 | \3 Publisher description \u http://www.loc.gov/catdir/description/els031/2002108919.html \y Publisher description |
| 856 | 4 | 1 | \3 Table of contents \u http://www.loc.gov/catdir/toc/els031/2002108919.html \y Table of contents |
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